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rev. 1.0 4/15 copyright ? 2015 by silicon laboratories SI5350C-B SI5350C-B f actory -p rogrammable a ny -f requency cmos c lock g enerator + pll features applications description the si5350c generates free-running and/or synchronized clocks selectable on each of its outputs. a dual pll + high resolution multisynth tm fractional divider architecture enables this user-definable cu stom timing device to generate any of the specified output frequenc ies at any of its outputs. this allows the si5350c to replace a combination of crystals, cr ystal oscillators, and synchronized cl ocks (pll). custom pin-controlled si5350c devices can be req uested using the clockbuilder web-based part number utility ( www.silabs.com/clockbuilder ). functional block diagram ? www.silabs.com/custom-timing ? generates up to 8 non-integer-related frequencies from 2.5 khz to 200 mhz ? exact frequency synthesis at each output (0 ppm error) ? glitchless frequency changes ? low output period jitter: < 70 ps pp, typ ? configurable spread spectrum selectable at each output ? user-configurable control pins: ?? output enable (oeb_0/1/2) ?? power down (pdn) ?? frequency select (fs_0/1) ?? spread spectrum enable (ssen) ?? loss of lock status (lolb) ? supports static phase offset ? rise/fall time control ? operates from a low-cost, fixed frequency crystal: 25 or 27 mhz ? separate voltage supply pins provide level translation: ?? core vdd: 1.8v, 2.5 v or 3.3 v ?? output vddo: 1.8 v, 2.5 v, or 3.3 v ? excellent psrr eliminates external power supply filtering ? very low power consumption (25 ma core, typ) ? available in 2 packages types: ?? 10-msop: 3 outputs ?? 20-qfn (4x4 mm): 8 outputs ? pcie gen 1 compliant ? supports hcsl compatible swing ? hdtv, dvd/blu-ray, set-top box ? audio/video equipment, gaming ? printers, scanners, projectors ? handheld instrumentation ? residential gateways ? networking/communication ? servers, storage ? xo replacement ordering information: see page 18 10-msop 20-qfn
SI5350C-B 2 rev. 1.0 table 1. the complete si5350/51 clock generator family part number i2c or pin frequency reference programmed? outputs datasheet si5351a-b-gt i2c xtal only blank 3 si5351-b si5351a-b-gm i2c xtal only blank 8 si5351-b si5351b-b-gm i2c xtal and/or voltage blank 8 si5351-b si5351c-b-gm i2c xtal and/or clkin blank 8 si5351-b si5351a-bxxxxx-gt i2c xtal only factory pre-programmed 3 si5351-b si5351a-bxxxxx-gm i2c xtal only factory pre-programmed 8 si5351-b si5351b-bxxxxx-gm i2c xtal and/or voltage factory pre-programmed 8 si5351-b si5351c-bxxxxx-gm i2c xtal and/or clkin factory pre-programmed 8 si5351-b si5350a-bxxxxx-gt pin xtal only factory pre-programmed 3 si5350a-b si5350a-bxxxxx-gm pin xtal only factory pre-programmed 8 si5350a-b si5350b-bxxxxx-gt pin xtal and/or voltage factory pre-programmed 3 si5350b-b si5350b-bxxxxx-gm pin xtal and/or voltage factory pre-programmed 8 si5350b-b SI5350C-Bxxxxx-gt pin xtal and/or clkin factory pre-programmed 3 SI5350C-B SI5350C-Bxxxxx-gm pin xtal and/or clkin factory pre-programmed 8 SI5350C-B notes: 1. xtal = 25/27 mhz, voltage = 0 to vdd, clkin = 10 to 100 mhz. "xxxxx" = unique custom code. 2. create custom, factory pre-programmed parts at www.silabs.com/clockbuilder.
SI5350C-B rev. 1.0 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.1. si5350c replaces multiple clocks and xos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.2. applying a reference clock at xt al input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.3. hcsl compatible outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4. configuring the si5350c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1. crystal inputs (xa, xb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2. external clock input pin (clkin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3. output clocks (clk0?clk7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4. programmable control pi ns (p0?p3) options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5. design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1. 20-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 5.2. 10-pin msop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 6. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 7. package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.1. 20-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.2. 10-pin msop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8. land pattern: 20-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 9. 10-pin msop package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 10. land pattern: 10-pin msop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 11. top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 11.1. 20-pin qfn top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11.2. top marking explana tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11.3. 10-pin msop top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.4. top marking explana tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
SI5350C-B 4 rev. 1.0 1. electrical specifications table 2. recommended operating conditions parameter symbol test condition min typ max unit ambient temperature t a ?40 25 85 c core supply voltage v dd 1.71 1.8 1.89 v 2.25 2.5 2.75 v 3.0 3.3 3.60 v output buffer voltage v ddox 1.71 1.8 1.89 v 2.25 2.5 2.75 v 3.0 3.3 3.60 v note: all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an op erating temperature of 25 c unless otherwise noted. vdd and vddox can be operated at independent voltages. power supply sequencing for vdd and vddox requires that all vddox be powered up either before or at the same time as vdd. table 3. dc characteristics (v dd = 1.8 v 5%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit core supply current* i dd enabled 3 outputs ? 20 35 ma enabled 8 outputs ? 25 45 ma power down (pdn = v dd )??50a output buffer supply current (per output)* i ddox c l =5pf ? 2.2 5.6 ma input current i p1-p3 pins p1, p2, p3 v p1-p3 <3.6v ??10 a i p0 pin p0 ? ? 30 a output impedance z oi 3.3 v vddo, default high drive. ?50? ? *note: output clocks less than or equal to 100 mhz.
SI5350C-B rev. 1.0 5 table 4. ac characteristics (v dd = 1.8 v 5%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit power-up time t rdy from v dd =v ddmin to valid output clock, c l =5pf, f clkn > 1 mhz ?210ms powerup time, pll bypass mode t byp from v dd =v ddmin to valid output clock, c l =5pf, f clkn >1mhz ?0.5 1 ms output enable time t oe from oeb assertion to valid clock output, c l = 5 pf, f clkn > 1 mhz ??10s output frequency transition time t freq f clkn >1mhz ? ? 10 s spread spectrum frequency deviation ss dev down spread selectable in 0.1% steps ?0.1 ? ?2.5 % spread spectrum modulation rate ss mod_c 30 31.5 33 khz table 5. input characteristics (v dd = 1.8 v 5%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max units crystal frequency f xtal 25 ? 27 mhz p0-p3 input low voltage v il_p0-3 ?0.1 ? 0.3 x v dd v p0-p3 input high voltage v ih_p0-3 v dd = 2.5 v or 3.3 v 0.7 x v dd ?3.60v v dd = 1.8 v 0.8 x v dd ?3.60v clkin frequency range f clkin 10 ? 100 mhz clkin input low voltage v il_clkin ?0.1 ? 0.3 x v dd v clkin input high voltage v ih_clkin 0.7 x v dd ?3.60v
SI5350C-B 6 rev. 1.0 table 6. output characteristics v dd = 1.8 v 5%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max units frequency range 1 f clk 0.0025 ? 200 mhz load capacitance c l f clk < 100 mhz ? ? 15 pf duty cycle dc f clk < 160 mhz, measured at v dd /2 45 50 55 % f clk > 160 mhz, measured at v dd /2 40 50 60 % rise/fall time t r /t f 20%?80%, c l = 5 pf ? 1 1.5 ns output high voltage v oh c l =5pf v dd ? 0.6 ? ? v output low voltage v ol ??0.6v period jitter 2,3 j per 20-qfn, 4 outputs running, 1 per vddo \ 40 95 ps, ? pk \ pk 10-msop or 20-qfn, all outputs running \ 70 155 ps, ? pk \ pk cycle-to-cycle jitter 2,3 j cc 20-qfn, 4 outputs running, 1 per vddo ?5090ps, pk 10-msop or 20-qfn, all outputs running ? 70 150 ps, pk notes: 1. only two unique frequencies above 112.5 mhz can be simultaneously output. 2. measured over 10k cycles. jitter is only specif ied at the default high drive strength (50 ? output impedance). 3. jitter is highly dependent on device frequency configuratio n. specifications represent a ?worst case, real world? frequency plan; actual performance may be substantially better. three-output 10msop package measured with clock outputs of 74.25, 24.576, and 48 mhz. eight-output 20qfn package measured with clock outputs of 33.33, 74.25, 27, 24.576, 22.5792, 28.322, 125, and 48 mhz. table 7. 25 mhz crystal requirements 1,2 parameter symbol min typ max unit crystal frequency f xtal ?25?mhz load capacitance c l 6?12pf equivalent series resistance r esr ??150 ? crystal max drive level d l 100 ? ? w notes: 1. crystals which require load capacitances of 6, 8, or 10 pf should use the device?s internal load capacitance for optimum performance. see register 183 bits 7:6. a crystal with a 12 pf lo ad capacitance requirement should use a combination of the internal 10 pf load capacitance in addition to external 2 pf load capacitance (e.g., by using 4 pf capacitors on xa and xb). 2. refer to ?an551: crystal selection guide? for more details.
SI5350C-B rev. 1.0 7 table 8. 27 mhz crystal requirements 1,2 parameter symbol min typ max unit crystal frequency f xtal ?27?mhz load capacitance c l 6?12pf equivalent series resistance r esr ??150 ? crystal max drive level d l 100 ? ? w notes: 1. crystals which require load capacitances of 6, 8, or 10 pf should use the device?s internal load capacitance for optimum performance. see register 183 bits 7:6. a crystal with a 12 pf lo ad capacitance requirement should use a combination of the internal 10 pf load capacitance in addition to external 2 pf load capacitance (e.g., by using 4 pf capacitors on xa and xb). 2. refer to ?an551: crystal selection guide? for more details. table 9. thermal characteristics parameter symbol test condition package value unit thermal resistance junction to ambient ? ja still air 10-msop 131 c/w 20-qfn 119 c/w thermal resistance junction to case ? jc still air 20-qfn 16 c/w table 10. absolute maximum ratings parameter symbol test condition value unit dc supply voltage v dd_max ?0.5 to 3.8 v input voltage vin_p1-3 pins p1, p2, p3 ?0.5 to 3.8 v vin_p0 p0 ?0.5 to (vdd+0.3) v vin_xa/b pins xa, xb ?0.5 to 1.3 v v junction temperature t j ?55 to 150 c note: permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
SI5350C-B 8 rev. 1.0 2. typical application 2.1. si5350c replaces mu ltiple clocks and xos the si5350c is a clock genera tion device that provides both synchron ous and free-running clocks for applications where power, board size, and cost are critical. an example application is shown in figure 1. any other combination is possible. figure 1. replacing multiple xtal/xos and plls with one si5350c 2.2. applying a refere nce clock at xtal input the si5350c can be driven with a clock signal through the xa input pin. this is especi ally useful when in need of generating clock outputs in two synchronization domains; one reference clock can be provided at the clkin pin and at xa. figure 2. si5350c driven by a clock signal ethernet phy usb controller hdmi port 28.322 mhz 48 mhz 125 mhz video/audio processor 74.25/1.001 mhz 24.576 mhz osc xa xb clk0 clk1 clk2 clk3 clk4 clk5 pll pll multi synth 0 multi synth 1 multi synth 2 74.25 mhz clkin 27 mhz si5350c multi synth 3 multi synth 4 multi synth 5 54 mhz free-running clocks synchronous clocks multi synth n multi synth 0 multi synth 1 pllb plla xa xb osc v in = 1 v pp 25/27 mhz note: float the xb input while driving the xa input with a clock 0.1 f
SI5350C-B rev. 1.0 9 2.3. hcsl compatible outputs the si5350c can be configured to support hcsl compatible swing when the vddo of the output pair of interest is set to 2.5 v (i.e., vddoa must be 2.5 v when using clk0/1; vddob must be 2.5 v for clk2/3 and so on). the circuit in the figure below must be applied to each of the two clocks used, and one of the clocks in the pair must also be inverted to generate a differential pair. figure 3. si5350c output is hcsl compatible multi synth n multi synth 0 multi synth 1 pllb plla osc note: the complementary -180 degree out of phase output clock is generated using the inv function r 1 511 ? 240 ? r 2 z o = 50 ? 0 ? hcsl clkin r 1 511 ? 240 ? r 2 z o = 50 ? 0 ?
SI5350C-B 10 rev. 1.0 3. functional description the architecture of the si5350c generates up to eight non -integer-related frequencies in any combination of free- running and/or synchronous clocks. a block diagram of both the 3-output and the 8-ou tput versions are shown in figure 4. free-running clocks are generated using the on-c hip oscillator + pll, and th e clock input pin (clkin) provides an external input reference fo r the synchronous cloc ks. each multisynth tm is configurable with two frequencies (f1_x, f2_x). this allows a pin controlled glit chless frequency change at each output (clk0 to clk5). figure 4. block diagrams of the si5350c devices with 3 and 8 outputs 10-msop multisynth 3 f1_2 f2_2 r2 fs multisynth 2 vdd gnd clk2 f1_0 f2_0 r0 fs multisynth 0 f1_1 f2_1 r1 fs multisynth 1 clk0 clk1 vddo f1_3 f2_3 r3 fs multisynth 3 f1_2 f2_2 r2 fs multisynth 2 20-qfn vdd gnd clk2 clk3 vddob control logic p2 p3 p0 p1 f1_0 f2_0 r0 fs multisynth 0 f1_1 f2_1 r1 fs multisynth 1 clk0 clk1 vddoa r6 r7 clk6 clk7 vddod f1_4 f2_4 r4 fs multisynth 4 f1_5 f2_5 r5 fs multisynth 5 clk4 clk5 vddoc f1_6 multisynth 6 f1_7 multisynth 7 control logic p0 pll a osc xa xb clkin pll a osc xa xb clkin pll b pll b
SI5350C-B rev. 1.0 11 4. configuring the si5350c the si5350c is a factory-programmed custom clock generato r that is user definable with a simple to use web- based utility ( www.silabs.com/clockbuilder ). the clockbuilder utility provides a simple graphica l interface that allows the user to enter input and output frequencies alon g with other custom features as described in the following sections. all synthesis calculations are automatica lly performed by clockbuilder to ensure an optimum configuration. a unique part number is assigned to each custom configuration. 4.1. crystal inputs (xa, xb) the si5350c uses an optional fixed-frequency non-pullabl e standard at-cut crystal as a reference to generate free-running output clocks. note that a xtal is not required for generating synchronous clocks that are locked to clkin. 4.1.1. crystal frequency the si5350c can operate using either a 25 mhz or a 27 mhz crystal. 4.1.2. internal xtal load capacitors internal load capacitors are provided to eliminate the need for external components when connecting a xtal to the si5350c. the total internal xtal load capacitance (c l ) can be selected to be 0, 6, 8 or 10 pf. xtals with alternate load capacitance requirements are supported us ing additional external load capacitance ? 2 pf (e.g., by using ? 4 pf capacitors on xa and xb) as shown in figure 5. figure 5. external xtal with optional load capacitors 4.2. external clo ck input pin (clkin) the external clock input is used as a reference for gen erating synchronous clocks. the input frequency can be specified from 10 to 100 mhz including fractional fr equencies (e.g., 74.25 mhz x 10 00/1001). the clockbuilder utility automatically determine s the exact synthesis ratio to guarantee an ou tput frequency wit h 0 ppm error with respect to its reference. 4.3. output clocks (clk0?clk7) the si5350c is orderable as a 3-out put (10-msop) or 8-output (20-qfn) clock generator. output clocks clk0 to clk5 can be ordered with two clock frequencies (f1_x, f2_x) which are selectable with the optional frequency select pins (fs0/1). see ?4.4.3. frequen cy select (fs_0, fs_1)? for more de tails on the operation of the frequency select pins. each output clock can select its reference for either of the plls. 4.3.1. output clock frequency outputs can be configured at any frequency from 2.5 khz up to 200 mhz. however, only two unique frequencies above 112.5 mhz can be simultaneously output. for ex ample, 125 mhz (clk0), 130 mhz (clk1), and 150 mhz (clkx) is not allowed. note that mu ltiple copies of frequencies above 1 12.5 mhz can be provided, for example, 125 mhz could be provided on four outputs (clks0-3) simultaneously with 130 mhz on four different outputs (clks4-7). xa xb optional internal load capacitance 0, 6, 8,10 pf optional additional external load capacitance (< 2 pf)
SI5350C-B 12 rev. 1.0 4.3.2. spread spectrum spread spectrum can be enabled on any of the clock output s that use plla as its reference. spread spectrum is useful for reducing electromagnetic interference (emi). e nabling spread spectrum on an output clock modulates its frequency, which effectively reduces the overall amplitude of its radiated energy. note that spread spectrum is not available on clocks synchronized to pllb. the si5350c supports several levels of spread spectr um allowing the designer to choose an ideal compromise between system performance and emi compliance. if the cl kin pin already has spread spectrum applied to it, it will get passed through to the outputs t hat are referenced to it . in this case, do not configure the synchronous outputs for spread spectrum as the device will er roneously try to add additional spread to them. an optional spread spec trum enable pin (ssen) is conf igurable to enable or disable the spread spectrum feature. see ?4.4.1. spread spectrum enable (ssen)? for details. figure 6. available spread spectrum profiles 4.3.3. invert/non-invert by default, each of the output clocks are generated in ph ase (non-inverted) with respect to each other. an option to invert any of the clock outputs is also available. 4.3.4. output state when disabled there are up to three output enable pins configurable on the si5350c as described in ?4.4.4. output enable (oeb_0, oeb_1, oeb_2)? . the output state when disabled fo r each of the outputs is configurable as output high, output low, or high-impedance. 4.3.5. powering down unused outputs unused clock outputs can be completely powered down to conserve power. 4.4. programmable cont rol pins (p0?p3) options up to four programmable control pins (p0-p3) are configur able allowing direct pin control of the following features: 4.4.1. spread spec trum enable (ssen) an optional control pin allows disabling the spread spec trum feature for all outputs that were configured with spread spectrum enab led. hold ssen low to disa ble spread spectrum. the ssen pin provides a convenient method of evaluating the effect of using spre ad spectrum clocks during emi compliance testing. 4.4.2. power down (pdn) an optional power down control pin allows a full shutdown of the si5350c to minimize power consumption when its output clocks are not being used. the si535 0c is in normal operation when the pdn pin is held low and is in power down mode when held high. power consumption when the device is in power down mode is indicated in table 3 on page 4. 4.4.3. frequency select (fs_0, fs_1) the si5350c offers the option of configuring up to tw o frequencies per clock output (clk0-clk5) for either free- running or synchronous clocks. this is a useful feature for applications that need to support more than one free- running or synchronous clock rate on the same output. an example of this is shown in figure 7. the fs pins select which frequency is generated from the clock output. in this example, fs0 selects the output frequency on clk0 f c reduced amplitude and emi down spread f c no spread spectrum center frequency amplitude
SI5350C-B rev. 1.0 13 and fs1 selects the frequency on clk1. figure 7. example of generating two clock frequencies from the same clock output up to two frequency select pins are available on the si 5350c. each of the frequency select pins can be linked to any of the clock outputs as shown in figure 8. for example, fs_0 can be linked to control clock frequency selection on clk0, clk3, and clk5; fs_1 can be used to control clock frequency selection on clk1, clk2, and clk4. any other combination is also possible. the freque ncy select feature is not available for clks 6 and 7. the si5350c uses control circuitry to ensure that freque ncy changes are glitchless. th is ensures that the clock always completes its last cycle before starting a new clock cycle of a different frequency. figure 8. example configuration of a pin-controlled frequency select (fs) 74.25 mhz or 74.25 1.001 mhz 27 mhz xa xb clk0 fs0 si5350c free-running clock fs1 clkin 24.576 mhz or 22.5792 mhz clk1 synchronous clock video/audio processor free-running frequency fs0 bit level 0 1 74.25 mhz f1_0: f2_0: 74.25 1.001 mhz synchronous frequency fs1 bit level 0 1 24.576 mhz f1_1: f2_1: 22.5792 mhz 54mhz clk0 clk1 clk2 clk3 clk4 clk5 clk6 clk7 fs_0 fs_1 fs_0 0 1 f1_0, f1_3, f1_5 f2_0, f2_3, f2_5 output frequency fs_1 0 1 f1_1, f1_2, f1_4 output frequency clkx frequency_a frequency_b full cycle completes before changing to a new frequency frequency_a new frequency starts at its leading edge glitchless frequency changes cannot be controlled by fs pins customizable fs control f2_1, f2_2, f2_4 multisynth 0 fs multisynth 1 fs multisynth 2 fs multisynth 3 fs multisynth 4 fs multisynth 5 fs
SI5350C-B 14 rev. 1.0 4.4.4. output enable (oeb_0, oeb_1, oeb_2) up to three output enable pins (oeb_0/1/2) are available on the si5350c. similar to the fs pins, each oeb pin can be linked to any of the output clocks. in the exam ple shown in figure 9, oeb_0 is linked to control clk0, clk3, and clk5; oeb_1 is linked to c ontrol clk6 and clk7, and oeb_2 is linked to control clk1, clk2, clk4, and clk5. any other combination is also possible. if more than one oeb pin is linked to the same clk output, the pin forcing a disable state will be dominant. clock ou tputs are enabled when t he oeb pin is held low. the output enable control circuitry ensures glitchless operati on by starting the output clock cycle on the first leading edge after oeb is asserted (oeb = low). when oeb is rele ased (oeb = high), the clock is allowed to complete its full clock cycle before going into a disabled state. this is shown in figure 9. when disabled, the output state is configurable as disabled high, disabled low, or disabled in high-impedance. figure 9. example configuration of a pin-controlled output enable 4.4.5. loss of lock (lolb) a loss of lock pin (lolb) is available to indicate the stat us of the synchronous clock outputs. the lolb pin is set to a high state when the synchronous clock outputs are lo cked to the clock input (clkin). this is the normal operating state for the synchronous cl ocks. the lolb pin will go low when th e reference clock at the clkin input is removed or if its frequency deviates by more than 2000 ppm from its defined center frequency. in this case, the synchronous clocks will continue to free- run. an option to disable the synchr onous output clocks during an lolb condition (lolb pin = low) is available. this only affects the clock outputs that were designated as synchronous clock outputs. an external pull up resistor (recommended 10 kohms) is needed on lolb as it is an open-drain signal, not a push-pull output. 4.5. design considerations the si5350c is a self-contained clock generator that requires very few exte rnal components. the following general guidelines are recommended to ensure optimum performance. 4.5.1. power supply decoupling/filtering the si5350c has built-in power supply filtering circuitry to help keep the number of external components to a minimum. all that is recommended is one 0.1 to 1.0 f dec oupling capacitor per power supply pin. this capacitor should be mounted as close to the vdd and vddo pins as possible without using vias. 4.5.2. power supply sequencing the vdd and vddox (i.e., vddo0, v ddo1, vddo2, vddo3) power supply pins have been separated to allow flexibility in output signal levels. power supply sequencing for vdd and vddox requires that all vddox be powered up either before or at the same time as vdd. unused vddox pins should be tied to vdd. clk0 clk1 clk2 clk3 clk4 clk5 clk6 clk7 oeb_0 oeb_1 oeb_0 0 1 clk enabled clk disabled output state oeb_2 oeb_1 0 1 clk enabled clk disabled output state oeb_2 0 1 clk enabled clk disabled output state clock continues until cycle is complete clkx oebx clock starts on the first leading edge glitchless output enable customizable oeb control oeb oeb oeb oeb oeb oeb oeb oeb
SI5350C-B rev. 1.0 15 4.5.3. external crystal the external crystal should be mounted as close to th e pins as possible using short pcb traces. the xa and xb traces should be kept away from other high-speed signal traces. see ?an5 51: crystal selection guide? for more details. 4.5.4. external crystal load capacitors the si5350c provides the option of using internal and exte rnal crystal load capacitors. if external load capacitors are used, they should be placed as close to the xa/xb pads as possible. see ?an551: crystal selection guide? for more details. 4.5.5. unused pins unused control pins (p0?p3) should be tied to gnd. unused clkin pin should be tied to gnd. unused xa/xb pins should be left floating. refer to "2.2 . applying a reference clock at xtal input" on page 8 when using xa as a clock input pin. unused output pins (clk0?clk7) should be left unconnected. 4.5.6. trace characteristics the si5350c features various output drive strength settings. it is recommended to configure the trace characteristics as shown in figure 10 when the default high output drive setting is used. figure 10. recommended trace characteristics with default drive strength setting z o = 50 ohms clk (optional resistor for emi management) r = 0 ohms
SI5350C-B 16 rev. 1.0 5. pin descriptions 5.1. 20-pin qfn figure 11. si5350c 20-qfn top view table 11. si5350c 20-qfn pin descriptions pin name pin number pin type function xa 1 i input pin for external xtal xb 2 i input pin for external xtal clkin 6 i external reference clock input clk0 13 o output clock 0 clk1 12 o output clock 1 clk2 9 o output clock 2 clk3 8 o output clock 3 clk4 19 o output clock 4 clk5 17 o output clock 5 clk6 16 o output clock 6 clk7 15 o output clock 7 p0 3 i user configurable pin 0. see 4.5.5 p1 4 i user configurable pin 1. see 4.5.5 p2 5 i user configurable pin 2. see 4.5.5 p3 7 i user configurable pin 3. see 4.5.5 vdd 20 p core voltage supply pin. see 4.5.2 vddoa 11 p output voltage supply pin for clk0 and clk1. see 4.5.2 vddob 10 p output voltage supply pin for clk2 and clk3. see 4.5.2 vddoc 18 p output voltage supply pin for clk4 and clk5. see 4.5.2 vddod 14 p output voltage supply pin for clk6 and clk7. see 4.5.2 gnd center pad p ground note: pin types: i = input, o = output, p = power 1 2 3 4 5 6 7 8 9 10 15 14 13 12 11 20 19 18 17 16 gnd pad xa xb p0 p1 p2 p3 clk3 clk2 vddob clkin clk6 clk5 vddoc clk4 vdd vddoa clk1 clk0 vddod clk7
SI5350C-B rev. 1.0 17 5.2. 10-pin msop figure 12. si5350c 10-msop top view table 12. si5350c 10-msop pin descriptions pin name pin number pin type function xa 2 i input pin for external xtal xb 3 i input pin for external xtal clkin 5 i external reference clock input clk0 10 o output clock 0 clk1 9 o output clock 1 clk2 6 o output clock 2 p0 4 i user configurable pin 0 . see 4.5.5 vdd 1 p core voltage supply pin . see 4.5.2 vddo 7 p output voltage supply pin for clk0, clk1, and clk2 . see 4.5.2 gnd 8 p ground note: pin types: i = input, o = output, p = power xa vdd p0 xb 2 1 4 3 clk1 clk0 vddo gnd 9 10 7 8 clkin 5 clk2 6
SI5350C-B 18 rev. 1.0 6. ordering information factory-programmed si5350c devices can be requested using the clock builder web-based utility available at: www.silabs.com/clockbuilder . a unique part number is assigned to each custom configuration as indicated in figure 13. figure 13. custom clock part numbers si5350 c bxxxxx xxx b = product revision b xxxxx = unique custom code. a five character code w ill be assigned for each unique custom configur ation gt =10-msop gm =20-qfn blank = bulk r = tape and reel for evaluation of si5350 c-bxxxxx-gm (20 qfn) evaluation boards si535x-b20qfn-evb
SI5350C-B rev. 1.0 19 7. package outline 7.1. 20-pin qfn figure 14. 20-pin qfn package drawing b d e a a1 e b seating plane l d2 e2 d2/2 e2/2 c a
SI5350C-B 20 rev. 1.0 table 13. package dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 ? 0.05 b 0.20 0.25 0.30 d 4.00 bsc d2 2.65 2.70 2.75 e 0.50 bsc e 4.00 bsc e2 2.65 2.70 2.75 l 0.35 0.40 0.45 aaa ? ? 0.10 bbb ? ? 0.10 ccc ? ? 0.08 ddd ? ? 0.10 notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline mo-220, variation vggd-5. 4. recommended card reflow profile is per t he jedec/ipc j-std-0 20 specification for small body components.
SI5350C-B rev. 1.0 21 7.2. 10-pin msop figure 15. 10-pin msop package drawing table 14. 10-msop package dimensions dimension min nom max a??1.10 a1 0.00 ? 0.15 a2 0.75 0.85 0.95 b 0.17 ? 0.33 c 0.08 ? 0.23 d 3.00 bsc e 4.90 bsc e1 3.00 bsc e 0.50 bsc l 0.400.600.80 l2 0.25 bsc q0?8 aaa ? ? 0.20 bbb ? ? 0.25 ccc ? ? 0.10 ddd ? ? 0.08 notes: 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec so lid state outline mo-137, variation c 4. recommended card reflow profile is per the jede c/ipc j-std-020 specification for small body components. ?
SI5350C-B 22 rev. 1.0 8. land pattern: 20-pin qfn figure 16 shows the recommended land pattern details for th e si5350 in a 20-pin qfn package. table 15 lists the values for the di mensions shown in the illustration. figure 16. 20-pin qfn land pattern
SI5350C-B rev. 1.0 23 table 15. pcb land pattern dimensions symbol millimeters c1 4.0 c2 4.0 e 0.50 bsc x1 0.30 x2 2.70 y1 0.80 y2 2.70 notes: general 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. this land pattern design is based on ipc- 7351 guidelines. solder mask design 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 4. a stainless steel, laser-cut and electro- polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 7. a 2x2 array of 1.10 x 1.10 mm openings on 1.30 mm pitch should be used for the center ground pad. card assembly 8. a no-clean, type-3 solder paste is recommended. 9. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
SI5350C-B 24 rev. 1.0 9. 10-pin msop package outline figure 17 illustrates the package details for the SI5350C-B in a 10-pin msop package. table 16 lists the values for the dimensions shown in the illustration. figure 17. 10-pin msop package drawing ?
SI5350C-B rev. 1.0 25 table 16. 10-msop package dimensions dimension min nom max a??1.10 a1 0.00 ? 0.15 a2 0.75 0.85 0.95 b 0.17 ? 0.33 c 0.08 ? 0.23 d 3.00 bsc e 4.90 bsc e1 3.00 bsc e 0.50 bsc l 0.400.600.80 l2 0.25 bsc q0?8 aaa ? ? 0.20 bbb ? ? 0.25 ccc ? ? 0.10 ddd ? ? 0.08 notes: 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec so lid state outline mo-137, variation c 4. recommended card reflow profile is per the jede c/ipc j-std-020 specification for small body components.
SI5350C-B 26 rev. 1.0 10. land pattern: 10-pin msop figure 18 shows the recommended land pattern details for the SI5350C-B in a 10-pin msop package. table 17 lists the values for the dimens ions shown in the illustration. figure 18. 10-pin msop land pattern ?
SI5350C-B rev. 1.0 27 table 17. pcb land pattern dimensions symbol millimeters min max c1 4.40 ref e 0.50 bsc g1 3.00 ? x1 ? 0.30 y1 1.40 ref z1 ? 5.80 notes: general 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per asme y14.5m-1994. 3. this land pattern design is based on the ipc-7351 guidelines. 4. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05mm. solder mask design 5. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 6. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 7. the stencil thickness shou ld be 0.125 mm (5 mils). 8. the ratio of stencil aperture to land pad size should be 1:1. card assembly 9. a no-clean, type-3 solder paste is recommended. 10. the recommended card reflow profile is per the jedec/ipc j-std- 020c specification for small body components.
SI5350C-B 28 rev. 1.0 11. top marking 11.1. 20-pin qfn top marking figure 19. 20-pin qfn top marking 11.2. top marking explanation mark method: laser pin 1 mark: filled circle = 0.50 mm diameter (bottom-left corner) font size: 0.60 mm (24 mils) line 1 mark format device part number si5350 line 2 mark format: tttttt = mfg code* manufacturing code from the assembly purchase order form. line 3 mark format: yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the assembly date. *note: the code shown in the ?tttttt? line does not correspond to the orderable part number or frequency plan. it is used for package assembly quality tracking purposes only.
SI5350C-B rev. 1.0 29 11.3. 10-pin msop top marking figure 20. 10-pin msop top marking 11.4. top marking explanation mark method: laser pin 1 mark: mold dimple (bottom-left corner) font size: 0.60 mm (24 mils) line 1 mark format device part number si5350 line 2 mark format: tttt = mfg code* line 2 from the ?markings? section of the assembly purchase order form. line 3 mark format: yww = date code assigned by the assembly house. y = last digit of current year (ex: 2013 = 3) ww = work week of assembly date. *note: the code shown in the ?tttt? line does not correspond to t he orderable part number or frequency plan. it is used for package assembly quality tracking purposes only.
SI5350C-B 30 rev. 1.0 d ocument c hange l ist revision 0.75 to revision 0.76 ? updated table 4 on page 5. ?? updated spread-spectrum frequency deviation parameter test condition and minimum spec value. ? updated ?6. ordering information? . ?? updated figure 13, ?custom clock part numbers,? on page 18. revision 0.76 to revision 1.0 ? extended frequency range from 8 mhz-160 mhz to 2.5 khz-200 mhz. ? added 1.8v vdd support. ? updated block diagrams for clarity. ? added complete si5350/51 family table, table 1. ? added top mark information. ? added landing pattern drawings. ? added powerup time, pll bypass, table 4. ? clarified down spread step sizes in table 4. ? updated max jitter specs (typ unchanged) in table 6. ? clarified power supply sequencing requirement, section 4.5.2. ? updated 4.4.5 loss of lock (lolb) section.
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